⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款采用28nm CMOS工艺的5GS/s、150mW、10位无SHA流水线/SAR混合ADC，旨在满足宽带卫星和有线接收器对低功耗、高速中分辨率直接采样ADC的需求。通过混合架构和优化设计，在高速下实现了低功耗和高线性度。
Rong Wu1, Hemasundar M. Geddada1, Yen-Jen Ko2, Yen Ding2, Chun-Sheng Huang2, Wei-Ta Shih2, Ming-Hung Hsieh2, Wei-Te Chou1, Tianwei Li1, Ayaskant Shrivastava1, Yi-Chun Chen1, Juo-Jung Hung1, Giuseppe Cusmai1, Jiangfeng Wu1, Mo M. Zhang1, Greg Unruh1, Ardie Venes1, Hung Sen Huang2, Chun-Ying Chen1 Broadcom, Irvine, CA, 2Broadcom, Hsinchu, Taiwan 1 The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (~5GS/s), mid-resolution (~10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive in terms of power efficiency and complexity compared to TI-pipelined ADCs [4], where the critical SNR, THD, and TI matching are only required in the MDACs resolving the MSBs. In this paper we report a hybrid of
Massimo Brandolini1, Young Shin1, Karthik Raviprakash1, Tao Wang1,