⚡ 本页包含 AI 生成的分析内容，仅供参考
本论文提出一款基于BiCMOS工艺的14位500MS/s开关电流流水线ADC，实现了90dB SFDR，用于多载波基站接收路径。通过开关电流技术克服时间交错ADC的失配问题，提高了集成度和线性度。
on data converters. To enable base stations with multi-carrier functionality, ADCs in the receive path need high sample rates with superior SFDR across 100s of MHz and several decades of input signal power. Furthermore, as the number of antennas increase, higher ADC integration is required to minimize board area, complexity, and cost. Time interleaving significantly eases sampling rate constraints but suffers from architectural drawbacks. Sub-ADC mismatches limit performance and the resulting distortion spurs complicate the system frequency planning. For example, timing skew of only 100fs for a 2×-interleaved ADC results in an SFDR of 76dB for a 500MHz input signal. Background calibration can track these mismatch artifacts [1] (as well as other ADC errors [2]), but incur a nonnegligible algorithm convergence time every time the ADC is enabled
Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Jesse Coulon,
Jake Hu, David Smith, Paul Landman, Mark Weaver Texas Instruments, Dallas, TX Wireless infrastructure imposes increasingly stringent requirements