A 0.5-to-32.75Gb/s Flexible-Reach Wireline Transceiver in 20nm CMOS

📋 论文概要

本文提出了一款在20nm CMOS工艺下实现的0.5至32.75Gb/s灵活范围有线收发器，旨在解决FPGA中高速背板收发器的性能可扩展性、高可用性和灵活架构等关键问题。通过创新的接收机及时钟电路技术，满足了通信和存储系统对带宽日益增长的需求。

💡 主要创新点

• 实现了从0.5Gb/s到32.75Gb/s的宽数据速率范围，支持灵活范围（flexible-reach）传输，适应不同信道损耗。
• 采用20nm CMOS工艺，利用先进节点实现了高速率与低功耗的平衡，并集成了接收机均衡和时钟数据恢复创新技术。

🏷 关键词

📄 原文摘要

Bruce Xu, Daniel Wu, Didem Turker, Hesam Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang Xilinx, San Jose, CA The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits. Figure 3.3.1 shows the transceiver architecture with reconfigurable clock generation consisting of two fractional-N LC PLLs per quad and a ring PLL per channel. Since the receiver and the transmitter (TX) require half-rate clock frequencies, the LC PLLs must cover a frequency range of 8 to 16.375GHz for data-rates of 16 to 32.75Gb/s. Lower data-rates are covered by dividing the

👥 作者与机构

Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup Jose,