A 128Gb 3b/cell V-NAND Flash Memory with 1Gb/s I/O Rate

📋 论文概要

本文提出了一款128Gb、每单元3比特（3b/cell）的V-NAND闪存芯片，实现了1Gb/s的I/O速率。该芯片通过垂直堆叠技术和3b/cell存储方案，解决了高密度、低成本和高性能存储的需求。

💡 主要创新点

• 采用3b/cell（TLC）的V-NAND架构，在垂直堆叠中实现高密度存储。
• 实现1Gb/s的高I/O速率，提升了闪存的数据传输性能。
• 通过优化的电路设计，在128Gb容量下保持成本效益和可靠性。

🏷 关键词

📄 原文摘要

Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, You-Se Kim, Hyun-Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jin-Ho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doo-Sub Lee, Ji-Ho Cho, Oh-Suk Kwon, Ji-Sang Lee, Moo-Sung Kim, Sang-Hyun Joo, Jae-Hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kye-Hyun Kyung, Jeong-Hyuk Choi Samsung Electronics, Hwaseong, Korea Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by

👥 作者与机构

Jae-Woo Im, Woo-Pyo Jeong, Doo-Hyun Kim, Sang-Wan Nam,