A 28nm CMOS Digital Fractional-N PLL with -245.5dB FOM and a Frequency Tripler For 802.11abgn/ac Radio

📋 论文概要

该论文提出了一种用于双频802.11abgn/ac无线电的28nm CMOS分数-N数字锁相环（PLL）设计，集成了低噪声晶体振荡器和频率三倍频器，实现了-245.5dB的优异FOM，有效解决了高调制阶数（如256-QAM）下对低相位噪声和低功耗的需求。

💡 主要创新点

• 采用数字PLL架构，结合1位ΔΣ调制器和频率三倍频器，在28nm CMOS工艺下实现了超低抖动和低功耗。
• 集成了低噪声晶体振荡器，进一步降低了整体相位噪声，提升系统性能。
• 通过优化的环路设计和数字校准技术，在满足802.11ac严格相位误差要求的同时，缩小了芯片面积并降低了功耗。

🏷 关键词

📄 原文摘要

Arvind Anumula Paramanandam, Anuranjan Jha, Norman Liu, Edwin Chan, Li Lin Marvell, Santa Clara, CA The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver good EVM performance. On the other hand, smaller area and lower power are always desired for lower cost and longer battery life. This work presents a 28nm CMOS LO design for dual-band 802.11abgn/ac radio with overall architecture shown in Fig. 9.4.1. It addresses the aforementioned challenges with a low-noise integrated XTAL oscillator, a fractional-N digital PLL utilizing 1) background reference clock-doubler duty-cycle error correction and quantization noise cancellation, 2) non-periodic DCO dithering and compensation, and an offset LO frequency plan based on a self-mixing frequency tripler. The PLL design achieves 0.36º integrated phase error or 0.17ps rms jitter while consuming 9.5mW, leading to a record FOM

👥 作者与机构

Xiang Gao, Luns Tee, Wanghua Wu, Kun-Seok Lee,