A 28Gb/s Multi-Standard Serial-Link Transceiver for Backplane Applications in 28nm CMOS

📋 论文概要

本文提出一款28Gb/s多标准串行链路收发器，采用28nm CMOS工艺，用于背板应用。通过14-tap自适应判决反馈均衡器（DFE）和5-tap前馈均衡器（FFE）补偿高达30dB的奈奎斯特损耗，避免了功耗高的模数转换器（ADC），实现了低功耗和面积高效。

💡 主要创新点

• 采用14-tap自适应DFE和5-tap FFE的均衡架构，在不使用ADC的情况下补偿30dB信道损耗。
• 支持OIF CEI-25G、CEI-28G、IEEE 802.3bj 100G-KR4等多标准，适用于背板应用。
• 在28nm CMOS工艺中实现低功耗和面积高效设计。

🏷 关键词

📄 原文摘要

in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-todigital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS. The transceiver block diagram is illustrated in Fig. 3.1.1. In the RX, after an inductor-shunted termination that overcomes electrostatic discharge (ESD)

👥 作者与机构

Bo Zhang, Karapet Khanoyan, Hamid Hatamkhani, Haitao Tong,

Kangmin Hu, Siavash Fallahi, Kambiz Vakilian, Anthony Brewster Broadcom, Irvine, CA Rapid internet traffic growth has fueled the demand for bandwidth