An 8.2-to-10.3Gb/s Full-Rate Linear Reference-less CDR Without Frequency Detector in 0.18µm CMOS

📋 论文概要

本文提出了一种在0.18µm CMOS工艺下实现的8.2-10.3Gb/s全速率线性参考less时钟数据恢复（CDR）电路，无需频率检测器。通过创新的架构设计，解决了传统参考less CDR在频率捕获与相位锁定转换过程中的鲁棒性问题，同时简化了系统复杂度。

💡 主要创新点

• 提出了一种无需频率检测器的全速率线性参考less CDR架构，避免了传统双环架构中频率捕获与相位锁定转换的鲁棒性问题。
• 在0.18µm CMOS工艺下实现了8.2-10.3Gb/s的宽工作范围，且无需外部参考时钟或电容阵列调谐。

🏷 关键词

📄 原文摘要

Broadcom, Irvine, CA 1 2 As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1-5]. However, the robustness of the transition between frequency acquisition and phase locking is always a concern, particularly for the linear CDR, which has an extremely limited capture range. Many works, based mainly on the Pottbacker frequency detector (FD) [1], have been reported. In [3] the capture range of the FD is only ±2.4% at 20Gb/s with no capacitor bank in the VCO; in [4] the capture range of the FD is about ±6.4% at 2.75Gb/s, with an 8b resolution of the capacitor bank in the VCO; in [5] the capture range is ±15% at 10Gb/s, with an 11b resolution of the capacitor bank. Thus the Pottbacker FD inherently suffers from a limited capture range, requiring a dedicated FD and a stringent tradeoff between the CDR capture range and the number of VCO bands.

👥 作者与机构

Sui Huang1, Jun Cao2, Michael M. Green1

University of California, Irvine, CA,