ISSCC 2014

2014

203 篇论文 · Digital Processors (19) · Wireless (19) · Data Converters (17) · Wireline I/O (17)

ISSCC 2014 Session 1 Plenary
Computing’s Energy Problem (and what we can do about it) Mark Horowitz
Departments of Electrical Engineering and Computer Science,
1. Introduction Technology scaling has decreased the cost of computing to the point where it can be included in almost anything. As a result, we now live in a world surrounded by computing devices. They power our searche
ISSCC 2014 Session 1 Plenary
In wireless communication, wireless LAN offers higher throughput, but its coverage is, in general, more limited than cellular (wireless WAN). This exchange between communication range and throughput has been identified earlier in the ISSCC 2013 trend tracking report [6][7], as shown in Figure
1.2.6. Before the Cloud 1.0 era, the data rate improved linearly. But since, Cloud 1.0, the data rate of WLAN and cellul
increased at a rate of approximately ten times every five years. Although the exact triggers of this data-rate increase are not easily identifiable, some possible contributors may be. First, there is the effect of the fo
ISSCC 2014 Session 1 Plenary
How Chips Pave the Road to the Higgs Particle and the Attoworld Beyond Erik H. M. Heijne
Instrumentation Physicist, CERN PH Department, Geneva, Switzerland
1.0 Introduction Scientific knowledge is the basis for new technology, but in return, new technology enables progress in science. One example has been the introduction of semiconductor imagers in astronomy. Telescopes no
ISSCC 2014 Session 1 Plenary
The Next Generation of Networked Experiences
Susie Wee, VP and CTO of Networked Experiences
Cisco Systems, San Jose, CA Abstract The evolution of networking technology has enabled impressive networked experiences, ranging from connected mobile context-aware experiences to immersive experiences provided by large
ISSCC 2014 Session 10 Digital Processors
A 28nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications
Martin Saint-Laurent1, Paul Bassett1, Ken Lin2, Yuhe Wang2, Son Le2,
Xufeng Chen2, Maen Alradaideh1, Tom Wernimont1, Kartik Ayyar3, Dan Bui1, Dwight Galbi1, Allan Lester1, Willie Anderson1 Qualcomm, Austin, TX, 2Qualcomm, San Diego, CA, Qualcomm, Bangalore, India 1 The pulsed latches, als
ISSCC 2014 Session 10 Digital Processors
A 28nm HPM Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores
Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda,
Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori Renesas Electronics, Tokyo, Japan The worldwide demand f
ISSCC 2014 Session 10 Digital Processors
Heterogeneous Multi-Processing Quad-Core CPU and
Dual-GPU Design for Optimal Performance, Power, and Thermal Tradeoffs in a 28nm Mobile Application
Processor Alice Wang1, Tsung-Yao Lin2, Shichin Ouyang3, Wei-Hung Huang2, Jidong Wang1, Shu-Hsin Chang2, Sheng-Ping Chen2, Chun-Hsiung Hu2, Jim C. Tai2, Koan-Sin Tan2, Meng-Nan Tsou2, Ming-Hsien Lee2, Gordon Gammie1, Chi-
ISSCC 2014 Session 10 AI / ML
A 1.22TOPS and 1.52mW/MHz Augmented Reality Multi-Core Processor with Neural Network NoC for HMD Applications
Gyeonghoon Kim, Youchang Kim, Kyuho Lee, Seongwook Park,
augmentation of images in a real-world environment. Wearable systems, such as head-mounted display (HMD) systems, have attempted to support real-time AR as a next generation UI/UX [1-2], but have failed, due to their lim
ISSCC 2014 Session 10 Digital Processors
A 90nm 20MHz Fully Nonvolatile Microcontroller for Standby-Power-Critical Applications
Noboru Sakimura1,2, Yukihide Tsuji1, Ryusuke Nebashi1, Hiroaki Honjo1,
Ayuka Morioka1, Kunihiko Ishihara1, Keizo Kinoshita2, Shunsuke Fukami2, Sadahiko Miura1, Naoki Kasai2, Tetsuo Endoh2, Hideo Ohno2, Takahiro Hanyu2, Tadahiko Sugibayashi1 NEC, Tsukuba, Japan, 2Tohoku University, Sendai, J
ISSCC 2014 Session 10 Digital Processors
A 0.74V 200µW Multi-Standard Transceiver Digital Baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 Personal Area Networks
Christian Bachmann, Gert-Jan van Schaik, Benjamin Busze,
Mario Konijnenburg, Yan Zhang, Jan Stuyt, Maryam Ashouei, Guido Dolmans, Tobias Gemmeke, Harmke de Groot Holst Centre/imec, Eindhoven, The Netherlands Ultra-low-power (ULP), short-range wireless connectivity is becoming
ISSCC 2014 Session 10 Digital Processors
A 105GOPS 36mm2 Heterogeneous SDR MPSoC with Energy-Aware Dynamic Scheduling and Iterative Detection-Decoding for 4G in 65nm CMOS
Benedikt Noethen, Oliver Arnold, Esther Pérez Adeva, Tobias Seifert,
Erik Fischer, Steffen Kunze, Emil Matúš, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, Jens-Uwe Schlüßler, Stefan Scholze, Dennis Walter, René Schüffny Technisc
ISSCC 2014 Session 10 Digital Processors
A Multi-Standard 2G/3G/4G Cellular Modem Supporting Carrier Aggregation in 28nm CMOS
Michael Breschel1, Peter Almers1, Fredrik Angsmark1,
Alberth Arvidsson1, Harald Bauer2, Kees van Berkel3, Joaquin Canovas1, Minh Do1, Anders Ekelund1, Torsten Larsson1, Bo Lincoln1, Magnus Malmberg1, Masao Naruse4, Masashi Onishi4, Christer Östberg1, Jean-Paul Smeets3, Mar
ISSCC 2014 Session 11 Data Converters
An Oversampled 12/14b SAR ADC with Noise Reduction and Linearity Enhancements Achieving up to 79.1dB SNDR
Pieter Harpe, Eugenio Cantatore, Arthur van Roermund
Autonomous wireless sensor nodes for cloud networks require ultra-low-power electronics. In particular, sensor readout interfaces need low-speed high-precision ADCs for capturing, e.g., bio-potential signals, environment
ISSCC 2014 Session 11 Data Converters
A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS
Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen
Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications
ISSCC 2014 Session 11 Data Converters
A 10b 0.6nW SAR ADC with Data-Dependent Energy Savings Using LSB-First Successive Approximation
Frank M. Yaul, Anantha P. Chandrakasan
ADCs used in medical and industrial monitoring often transduce signals with short bursts of high activity followed by long idle periods. Examples include biopotential, sound, and accelerometer waveforms. Current approach
ISSCC 2014 Session 11 Data Converters
A 1.5mW 68dB SNDR 80MS/s 2× Interleaved SARAssisted Pipelined ADC in 28nm CMOS
Frank van der Goes1, Chris Ward1, Santosh Astgimath2, Han Yan1,
sampling speed of recently reported SAR ADCs have increased to 11+ ENOB at 50 to 100MS/s [1,2]; however, power efficiency has unfortunately suffered when compared to lower-resolution, lower-speed ADCs. This design target
ISSCC 2014 Session 11 Data Converters
A 100MS/s 10.5b 2.46mW Comparator-less Pipeline ADC Using Self-Biased Ring Amplifiers
Yong Lim1,2, Michael P. Flynn1
Samsung Electronics, Yongin, Korea 1 2 Pipelined ADCs require accurate amplification; however traditional OTAs limit power efficiency since they require high quiescent current for slewing. In addition, it is difficult to
ISSCC 2014 Session 11 Data Converters
A 21mW 15b 48MS/s Zero-Crossing Pipeline ADC in 0.13µm CMOS with 74dB SNDR
Dong-Young Chang1, Carlos Muñoz2, Denis Daly2, Soon-Kyun Shin2,
Kevin Guay2, Thomas Thurston2, Hae-Seung Lee3, Kush Gulati1, Matthew Straayer2 Maxim Integrated, San Jose, CA, Maxim Integrated, North Chelmsford, MA, 3 Massachusetts Institute of Technology, Cambridge, MA 1 2 Pipeline A
ISSCC 2014 Session 11 Data Converters
A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz
Hans Van de Vel, Joost Briaire, Corné Bastiaansen, Pieter van Beek,
Govert Geelen, Harrie Gunnink, Yongjie Jin, Mustafa Kaba, Kerong Luo, Edward Paulus, Bang Pham, William Relyveld, Peter Zijlstra Integrated Device Technology, Eindhoven, The Netherlands Advanced wireless cellular infrast
ISSCC 2014 Session 12 Sensors
3D Ultrasonic Gesture Recognition
Richard J. Przybyla1, Hao-Yen Tang1, Stefon E. Shelton2,
David A. Horsley2, Bernhard E. Boser1 University of California, Berkeley, CA, 2University of California, Davis, CA 1 Optical 3D imagers for gesture recognition suffer from large size and high power consumption. Their per
ISSCC 2014 Session 12 Sensors
3D Gesture-Sensing System for Interactive Displays Based on Extended-Range Capacitive Sensing
Yingzhe Hu, Liechao Huang, Warren Rieutort-Louis,
Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma Princeton University, Princeton, NJ Capacitive touch screens have enabled compelling interfaces for displays [1]. Three-dimensional (3D) sensing, where use
ISSCC 2014 Session 12 Sensors
A 240Hz-Reporting-Rate 143×81 Mutual-Capacitance Touch-Sensing Analog Front-End IC with 37dB SNR for 1mm-Diameter Stylus
Mutsumi Hamaguchi1, Akira Nagao2, Masayuki Miyamoto2
Sharp, Tenri, Japan 1 2 Realization of a mutual-capacitance touch-sensing system spanning over 30 inches is not a straightforward task, because the SNRs of conventional sequential drive controllers degrade as the number
ISSCC 2014 Session 12 Sensors
A 1mm-Pitch 80×80-Channel 322Hz-Frame-Rate Touch Sensor with Two-Step Dual-Mode Capacitance Scan
Noriyuki Miura1, Shiro Dosho2, Satoshi Takaya1, Daisuke Fujimoto1,
322Hz-frame-rate touch sensor is reported. Multiple touch points are detected by a two-step dual-mode capacitance scan, where self- and mutual-capacitance measurements are hierarchically performed in two steps to reduce
ISSCC 2014 Session 12 Sensors
2D Coded-Aperture-Based Ultra-Compact Capacitive Touch-Screen Controller with 40 Reconfigurable Channels
Hongjae Jang1, Hyungcheol Shin2, Seunghoon Ko1,
For example, the 4×4 basis shown in Fig. 12.5.2 has a TX code unbalance of +2 and an RX steering ratio of 3:1, requiring CF larger than 6C0 even without room for noise margin. The offset canceller cancels out the common-
ISSCC 2014 Session 12 Sensors
A 160nW 63.9fJ/conversion-step Capacitance-toDigital Converter for Ultra-Low-Power Wireless Sensor Nodes
Hyunsoo Ha1, Dennis Sylvester2, David Blaauw2, Jae-Yoon Sim1
University of Michigan, Ann Arbor, MI 1 2 Recent advances in nW-level wireless sensor nodes have created opportunities in emerging applications such as bio-implantable telemetry, smart healthcare, and environmental monit
ISSCC 2014 Session 12 Sensors
A 0.85V 600nW All-CMOS Temperature Sensor with an Inaccuracy of ±0.4°C (3σ) from -40 to 125°C
Kamran Souri1, Youngcheol Chae2, Frank Thus3, Kofi Makinwa1
Yonsei University, Seoul, Korea, 3 NXP Semiconductors, Eindhoven, The Netherlands 1 2 This paper describes an all-CMOS temperature sensor intended for RFID applications that achieves both sub-1V operation and high accura
ISSCC 2014 Session 12 Sensors
A BJT-Based CMOS Temperature Sensor with a 3.6pJ·K2-Resolution FoM
Ali Heidary1,2,3, Guijie Wang1,2, Kofi Makinwa2, Gerard Meijer1,2,4
Delft University of Technology, Delft, The Netherlands, 3 Guilan University, Rasht, Iran, 4 SensArt, Delft, The Netherlands 1 2 This paper presents a precision BJT-based temperature sensor implemented in standard CMOS. I
ISSCC 2014 Session 12 Sensors
A 1.55×0.85mm2 3ppm 1.0µA 32.768kHz MEMS-Based Oscillator
Samira Zali Asl1,2, Shouvik Mukherjee1, Will Chen1, Kimo Joo1,
Rajkumar Palwai1, Niveditha Arumugam1, Preston Galle1, Meghan Phadke1, Charles Grosjean1, Jim Salvia1, Haechang Lee1, Sudhakar Pamarti3, Terri Fiez2, Kofi Makinwa4, Aaron Partridge1, Vinod Menon1 SiTime, Sunnyvale, CA, O
ISSCC 2014 Session 13 Memory
A 1Gb 2GHz Embedded DRAM in 22nm Tri-Gate CMOS Technology
Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh,
Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang Intel, Hillsboro, OR CMOS technology scaling continues to drive higher levels of integration in VLS
ISSCC 2014 Session 13 Memory
A 14nm FinFET 128Mb 6T SRAM with VMINEnhancement Techniques for Low-Power Applications
Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang,
Jaeho Park, Sunghyun Park, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyuhong Kim, Jintae Kim, Youngkeun Lee, Kee Sup Kim, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi Samsung Electronics, Yon
ISSCC 2014 Session 13 Memory
20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists
Makoto Yabuuchi, Yasumasa Tsukamoto,
local variation in transistor characteristics, which has been deteriorating the operation margin of SRAM. This trend necessitates assist circuits for SRAM to increase the immunity against variations, and many papers in t
ISSCC 2014 Session 13 Memory
A 7ns-Access-Time 25µW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current
Toshikazu Fukuda1, Koji Kohara1, Toshiaki Dozaka1,
Yasuhisa Takeyama1, Tsuyoshi Midorikawa1, Kenji Hashimoto2, Ichiro Wakiyama2, Shinji Miyano1, Takehiko Hojo1 Toshiba, Kawasaki, Japan, 2Toshiba Microelectronics, Kawasaki, Japan 1 Battery lifetime is the key feature in t
ISSCC 2014 Session 13 Memory
A 16nm 128Mb SRAM in High-κ Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications
Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao,
Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang TSMC, Hsinchu, Taiwan FinFET technology has become a mainstream te
ISSCC 2014 Session 13 Memory
A 28nm 400MHz 4-Parallel 1.6Gsearch/s 80Mb Ternary CAM
Koji Nii1, Teruhiko Amano2, Naoya Watanabe2, Minoru Yamawaki3,
enable signal (MLPRE) is negated, the ML is discharged (search miss) or maintains the VDD level (match). The ML reference voltage REFVD is generated by charge sharing between REFVD and REFVS nodes, lowering to 700mV and
ISSCC 2014 Session 13 Memory
A Reconfigurable Sense Amplifier with Auto-Zero Calibration and Pre-Amplification in 28nm CMOS
Bharan Giridhar, Nathaniel Pinckney, Dennis Sylvester, David Blaauw
High-performance SRAMs are critical elements in microprocessors and SoCs. Fast and robust bitline sensing is a key requirement in such memories. With process scaling, increased mismatch in the sense amplifier (SA) circui
ISSCC 2014 Session 13 Memory
A 32kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS
Fabio Frustaci1,2, Mahmood Khayatzadeh2, David Blaauw2,
Singapore 1 2 Voltage scaling is widely used to improve SRAM energy efficiency [1-2], particularly in mobile systems with tight power budgets. The resulting energy benefits are limited by the minimum voltage ensuring err
ISSCC 2014 Session 14 mm-Wave
A 0.9V 20.9dBm 22.3%-PAE E-Band Power Amplifier with Broadband Parallel-Series Power Combiner in 40nm CMOS
Dixian Zhao, Patrick Reynaert
The 71-to-76GHz and 81-to-86GHz bands (known as E-band) exhibit low atmospheric attenuation and are allocated by FCC and CEPT for long-haul transmission. They enable multi-Gb/s fixed-link services such as fiber extension
ISSCC 2014 Session 14 mm-Wave
A 79GHz Phase-Modulated 4GHz-BW CW Radar TX in 28nm CMOS
Vito Giannini1, Davide Guermandi1, Qixian Shi1,2, Kristof Vaesen1,
Bertrand Parvais1, Wim Van Thillo1, André Bourdoux1, Charlotte Soens1, Jan Craninckx1, Piet Wambacq1,2 imec, Leuven, Belgium, Vrije Universiteit Brussel, Brussels, Belgium 1 2 Millimeter-Wave radar sensors perform accura
ISSCC 2014 Session 14 mm-Wave
A Push-Pull mm-Wave Power Amplifier with <0.8° AM-PM Distortion in 40nm CMOS
Shailesh Kulkarni, Patrick Reynaert
Millimeter-Wave standards like IEEE 802.15.3c and the new 802.11ad have classifications of their PHY to support single-carrier mode and more complex OFDM mode (high-speed interface) with high peak-to-average ratio (PAPR)
ISSCC 2014 Session 14 mm-Wave
A Class F-1/F 24-to-31GHz Power Amplifier with
40.7% Peak PAE, 15dBm OP1dB, and 50mW Psat in, 0.13µm SiGe BiCMOS
using PA arrays and by combining individual PA output powers either on chip with linear combiners or in free space with antenna arrays [1,2]. Therefore, the output power of a PA element can be compromised by the array si
ISSCC 2014 Session 14 mm-Wave
A 0.53THz Reconfigurable Source Array with up to 1mW Radiated Power for Terahertz Imaging Applications in 0.13µm SiGe BiCMOS
Ullrich R. Pfeiffer1, Yan Zhao1, Janusz Grzyb1, Richard Al Hadi1,
silicon-based THz video cameras have been demonstrated for industrial, surveillance, scientific, and medical applications in the THz range (300GHz to 3THz) [1]. Such camera implementations favor pixels with antennacouple
ISSCC 2014 Session 14 mm-Wave
A Scalable THz 2D Phased Array with +17dBm of EIRP at 338GHz in 65nm Bulk CMOS
Yahya Tousi, Ehsan Afshari
There is an untapped market for integrated high-resolution imaging and spectroscopy at mm-Wave and THz frequencies. Some novel approaches have been recently proposed to render on-chip signal generation and transmission a
ISSCC 2014 Session 14 mm-Wave
A 300GHz Frequency Synthesizer with 7.9% Locking Range in 90nm SiGe BiCMOS
Pei-Yuan Chiang1, Zheng Wang1, Omeed Momeni2, Payam Heydari1
University of California, Davis, CA 1 2 The THz/sub-mm-Wave band is known to provide unique applications in spectroscopy, imaging and high-data-rate wireless communication. An accurate THz source is essential in coherent
ISSCC 2014 Session 14 mm-Wave
A 247-to-263.5GHz VCO with 2.6mW Peak Output Power and 1.14% DC-to-RF Efficiency in 65nm Bulk CMOS
Muhammad Adnan, Ehsan Afshari
Signal generation at mm-Wave-to-THz frequencies is attractive because of its applications in bio-sensing, spectroscopy, detection of concealed weapons, as well as high-data-rate communication. CMOS is considered a potent
ISSCC 2014 Session 15 Digital Circuits
A 0.0066mm2 780µW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative PhaseCoupled Oscillator Using Edge-Injection Technique
Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon,
digital systems. All-digital PLLs have been proposed to address design issues in conventional analog PLLs. However, current all-digital PLLs require custom circuit design, and therefore cannot fully leverage advanced aut
ISSCC 2014 Session 15 Digital Circuits
A 0.012mm2 3.1mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Frequency Divider
Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin,
recently due to their compatibility with advanced CMOS technology. However, there are two critical factors hindering their uptake in SoC products. One factor is that a digitally controlled oscillator (DCO) is highly sens
ISSCC 2014 Session 15 Digital Circuits
A 2.4GHz ADPLL with Digital-Regulated Supply-Noise-Insensitive and Temperature-Self-Compensated Ring DCO
Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang
(RVCOs) ([oscillation frequency change %] / [VDD change %] typically lies in the range from 1 to 2 [1]), an LDO has to provide over 40dB power-supply-rejection ratio (PSRR) to maintain VCO phase noise. However, the volta
ISSCC 2014 Session 15 Digital Circuits
A 20-to-1000MHz ±14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS
Ahmed Elkholy1, Amr Elshazly2, Saurabh Saxena1,
digital, and mixed-signal functions. They contain a wide variety of modules such as multicore processors, memories, I/O interfaces, power management, and wireless transceivers. Each module has its own unique clock requir
ISSCC 2014 Session 16 Digital Processors
A 340mV-to-0.9V 20.2Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16×16 Network-onChip in 22nm Tri-Gate CMOS
Gregory Chen, Mark A. Anders, Himanshu Kaul, Sudhir K. Satpathy,
Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De Intel, Hillsboro, OR Energy-efficient networks-on-chip (NoCs) are key enablers for exa-scale computation by shifting power budge
ISSCC 2014 Session 16 Digital Processors
A 0.19pJ/b PVT-Variation-Tolerant Hybrid Physically Unclonable Function Circuit for 100% Stable Secure Key Generation in 22nm CMOS
Sanu K. Mathew, Sudhir K. Satpathy, Mark A. Anders, Himanshu Kaul,
Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram K. Krishnamurthy, Vivek De Intel, Hillsboro, OR Physically unclonable function (PUF) circuits are low-cost cryptographic primitives used for generation