⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种基于MDLL的分数-N频率合成器，采用1位TDC技术，在1.7GHz输出频率下实现了1.4ps RMS积分抖动和3mW功耗，解决了电感式频率合成器在噪声和功耗方面的挑战。
Salvatore Levantino, Carlo Samori, Andrea L. Lacaita Politecnico di Milano, Milan, Italy The introduction of inductorless frequency synthesizers into standardized wireless systems still requires a high level of innovation in order to achieve the stringent requirements of low noise and low power consumption. Synthesizers based on the so-called multiplying delay-locked loop (MDLL) represent one of the most promising architectures in this direction [1-3]. An MDLL resembles a ring oscillator, in which the signal edge traveling along the delay line is periodically refreshed by a clean edge of the reference clock. In this manner, the phase noise of the ring oscillator is filtered up to half the reference frequency and the total output jitter is reduced significantly. Unfortunately, the concept of MDLL, and in general of injection locking (IL), is inherently limited to integer-N synthesis, which makes it unacceptable in practical RF systems. A first extension
Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin,