A 5.67mW 9Gb/s DLL-Based Reference-less CDR with Pattern-Dependent Clock-Embedded Signaling for Intra-Panel Interface

📋 论文概要

本文提出了一种基于DLL的无参考时钟数据恢复电路，采用模式依赖的时钟嵌入信号技术，用于面板内接口。该设计在9Gb/s速率下仅消耗5.67mW功耗，解决了传统CDR需要参考时钟或额外时钟通道的问题。

💡 主要创新点

• 提出模式依赖的时钟嵌入信号（PD-CES）技术，利用数据流中的特定模式嵌入时钟信息，实现宽范围时钟捕获。
• 采用基于DLL的CDR架构，无需PLL或外部参考时钟，降低了功耗和复杂度。
• 实现了9Gb/s高速率下仅5.67mW的低功耗性能，适用于高分辨率、高帧率的大尺寸显示接口。

🏷 关键词

📄 原文摘要

Samsung Electronics, Yongin, Korea 1 2 Point-to-point data transmission with clock-embedded signaling (CES) has been generally adopted in intra-panel interfaces, which need to support fine resolution, high frame rate, and large display size. Since CES embeds the clocktransition information in the data stream, it enables wide-range clock acquisition with PLL-based [1,2] or DLL-based [3-5] clock-and-data recovery (CDR) schemes. It also offers additional benefits of reduced EMI and low cost by eliminating the need for an additional clock channel or reference signal. For clock recovery, however, CES transmits a significant number of extra bits attached to each data packet to carry clock transition information. The number of extra bits is at least three [4] or four [3], sufficient to reduce the effect of inter-symbol interference (ISI) on clock transitions from adjacent random data patterns, providing cleaner reference to the clock recovery circuit. The repeated

👥 作者与机构

Dong Hoon Baek1,2, Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1

Pohang University of Science and Technology, Pohang, Korea,