20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists

📋 论文概要

本文针对20nm工艺下SRAM因晶体管局部变异导致的读/写操作裕度下降问题，提出了一种基于字线电压调整（Wordline-Voltage-Adjustment）的读写辅助电路。该方案通过动态调节字线电压来增强单端口和双端口SRAM的稳定性，适用于高密度嵌入式存储器。

💡 主要创新点

• 提出字线电压调整系统，通过动态改变字线电平同时改善读和写操作裕度，无需额外辅助电容或复杂时序。
• 在20nm工艺下实现高密度单端口和双端口SRAM，有效应对NMOS与PMOS器件变异差异增大的挑战。

🏷 关键词

📄 原文摘要

local variation in transistor characteristics, which has been deteriorating the operation margin of SRAM. This trend necessitates assist circuits for SRAM to increase the immunity against variations, and many papers in this area [1-4] have been published. In this paper, we present an assist circuit suitable for the SRAMs in 20nm generation. Figure 13.3.1 compares local variations of SRAM cell transistors, pass-gate NMOS (PG), pull-down NMOS (PD) and pull-up PMOS (PU) for 28 and 20nm, showing degradation as the process advances. Noticeably, the NMOS transistors become worse than PMOS, which causes degradation in SRAM operating margin since SRAM characteristics such as static noise margin (SNM) are more sensitive to NMOS than PMOS. Figure 13.3.1 also shows the operational window enclosed by read and write immunity

👥 作者与机构

Makoto Yabuuchi, Yasumasa Tsukamoto,

Masao Morimoto, Miki Tanaka, Koji Nii Renesas Electronics, Tokyo, Japan Scaling of process technology is inevitably accompanied by the increase of