A 0.25pJ/b 0.7V 16Gb/s 3-Tap Decision-Feedback Equalizer in 65nm CMOS

📋 论文概要

本文提出了一种在65nm CMOS工艺下实现的3抽头判决反馈均衡器（DFE），能够在0.7V低供电电压下达到16Gb/s的数据速率，并实现0.25pJ/b的高能效。该设计解决了高速串行链路中低压下均衡电路的能效挑战。

💡 主要创新点

• 提出了一种低电压（0.7V）下工作的3抽头DFE架构，实现了16Gb/s的高速数据传输。
• 通过电路设计优化，在65nm CMOS节点达到了0.25pJ/b的极低能耗，显著提升了能效。
• 针对>10Gb/s串行链路中的均衡难题，实现了低电压下的高性能均衡，适用于功耗受限系统。

🏷 关键词

📄 原文摘要

Texas A&M University, College Station, TX, 3 Fudan University, Shanghai, China 1 2 Supply-voltage scaling has become one of the most effective methods to improve the energy efficiency of power-constrained systems, motivating its application towards high-performance I/O links [1]. Due to the accelerating need for more off-chip I/O bandwidth, it is desirable to provide both higher data rate and low-VDD operation to achieve optimal energy efficiency. Unfortunately, efficient implementations of equalization circuits are one of the major challenges faced in >10Gb/s serial-link systems that attempt to incorporate reduced-supply operation. For example, a continuous-time linear equalizer (CTLE), due to its analog nature, exhibits a rapid degradation in gain/bandwidth and only linear power scaling when operating at low VDD. Decision-feedback equalizers (DFEs) also have to make significant compromise of speed from longer delay in the

👥 作者与机构

Rui Bai1, Samuel Palermo2, Patrick Yin Chiang1,3

Oregon State University, Corvallis, OR,