A Pin- and Power-Efficient Low-Latency 8-to-12Gb/s/wire 8b8w-Coded SerDes Link for High-Loss Channels in 40nm Technology

📋 论文概要

该论文提出了一种采用8b8w编码的SerDes链路，在40nm工艺下实现8-12Gb/s/wire的数据速率，旨在解决高损耗信道下带宽需求增加的问题，同时降低引脚数和功耗，并实现低延迟。

💡 主要创新点

• 提出8b8w编码方案，通过8线传输8比特数据，相比传统差分对减少了引脚数，提升了引脚效率。
• 实现了低延迟设计，适用于对延迟敏感的互连场景，同时保持高能效和低功耗。

🏷 关键词

📄 原文摘要

Fabio Licciardello1, Kia Salimi1, Hugo Santos1, Amin Shokrollahi1, Roger Ulrich1, Christoph Walter1, John Fox2, Peter Hunt2, John Keay2, Richard Simpson2, Andy Stewart2, Giuseppe Surace2, Harm Cronie3 Kandou Bus, Lausanne, Switzerland, Kandou Bus, Northampton, United Kingdom, 3 Lausanne, Switzerland 1 2 The continuing demand for higher bandwidth in serial interconnects has pushed the symbol rate of differential lanes into the high-insertion-loss region of channels. Multi-level signaling such as differential PAM-4 [1] has been used to mitigate the loss of electrical channels by lowering the signal spectrum. Such an approach suffers from lower SNR tolerance as well as higher susceptibility to crosstalk and ISI as compared to differential signaling (DS). Coded differential approaches have been reported [2] to mitigate ISI. Our approach is a generalization of DS in which ternary values are transmitted on an 8-wire bus.

👥 作者与机构

Anant Singh1, Dario Carnelli1, Altay Falay1, Klaas Hofstra1,