A Multi-Granularity FPGA with Hierarchical Interconnects for Efficient and Flexible Mobile Computing

📋 论文概要

本文提出了一种多粒度FPGA，通过分层互连结构实现高效灵活移动计算，解决了传统专用加速器导致的暗硅和缺乏灵活性的问题。

💡 主要创新点

• 提出多粒度逻辑块混合架构，结合不同粒度处理单元提升能效和灵活性。
• 设计分层互连网络，优化数据传输延迟和功耗，适应移动计算需求。

🏷 关键词

📄 原文摘要

Following the rapid expansion of mobile computing in the past decade, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy efficiency. An increasing number of accelerators in power-limited SoCs results in large regions of “dark silicon.” Such accelerators lack flexibility, thus any design change requires a SoC re-spin, significantly impacting cost and timeline. To address the need for efficiency and flexibility, this work presents a multi-granularity FPGA suitable for mobile computing. Occupying 20.5mm2 in 40nm CMOS, the chip incorporates 2,760 fine-grained configurable logic blocks (CLBs) with 11,040 6-input look-up-tables (LUTs) for random logic, basic arithmetic, shift registers, and distributed memories, 42 medium-grained 48b DSP processors for MAC and SIMD operations, 16 32K×1b to 512×72b reconfigurable block RAMs, and 2 coarsegrained kernels: a 64-8192-point fast Fourier transform (FFT) processor and a

👥 作者与机构

Cheng C. Wang1, Fang-Li Yuan1, Tsung-Han Yu2, Dejan Markovic1

University of California, Los Angeles, CA, 2Qualcomm, Irvine, CA