A 0.0066mm2 780µW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative PhaseCoupled Oscillator Using Edge-Injection Technique

📋 论文概要

本文提出了一种全可综合的锁相环（PLL），采用电流输出DAC和插值相位耦合振荡器，实现了0.0066mm²的芯片面积和780µW的低功耗，解决了现有全可综合PLL功耗高、面积大的问题。

💡 主要创新点

• 首次实现全可综合PLL，无需任何定制电路设计，完全兼容自动化数字设计流程。
• 采用电流输出DAC和插值相位耦合振荡器，替代传统大量并行三态缓冲器/反相器，显著降低功耗和面积。

🏷 关键词

📄 原文摘要

digital systems. All-digital PLLs have been proposed to address design issues in conventional analog PLLs. However, current all-digital PLLs require custom circuit design, and therefore cannot fully leverage advanced automated digital design flows. While fully synthesizable PLLs [1, 2, 3] have been reported, they suffer from high power consumption and large area. This arises because each stage of the ring needs to have a large number of parallel tristate buffers/inverters in order to achieve the necessary frequency resolution. Moreover, custom-designed cells are required in prior synthesizable PLLs [2, 3], introducing additional place-and-route (P&R) steps, leading to poor portability, integration, and scalability. To address these issues, this paper proposes a fully

👥 作者与机构

Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon,

Satoshi Kondo, Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan Phase-locked loops (PLLs) are widely used for clock generation in modern