⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文介绍了一款支持2G/3G/4G多标准及载波聚合的蜂窝调制解调器，采用28nm CMOS工艺实现。通过可编程DSP架构和SIMD操作，解决了多标准兼容与高吞吐量需求之间的矛盾。
Alberth Arvidsson1, Harald Bauer2, Kees van Berkel3, Joaquin Canovas1, Minh Do1, Anders Ekelund1, Torsten Larsson1, Bo Lincoln1, Magnus Malmberg1, Masao Naruse4, Masashi Onishi4, Christer Östberg1, Jean-Paul Smeets3, Mario Vergara Escobar1, Juergen Voelkl2, Emma Wittenmark1 Ericsson, Lund, Sweden, 2Ericsson, Nuremberg, Germany, Ericsson, Eindhoven, The Netherlands, 4Ericsson, Yokohama, Japan The EVP is a programmable DSP supporting up to 100 operations per clock cycle at a rate of 416MHz. This high throughput is the result of executing multiple single-instruction-multiple-data (SIMD) operations (256b wide), as well as multiple scalar operations in a very-long instruction word (VLIW) fashion, as illustrated in Fig. 10.8.3. Compared to [3], the current EVP not only operates on fixed-point data, but also on floating-point data. The 32+4 floating-point multipliers support 8+1 complex multiply-accumulate operations every clock
Michael Breschel1, Peter Almers1, Fredrik Angsmark1,