A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS

📋 论文概要

该论文提出了一款64路交织的8位SAR ADC，在32nm数字SOI CMOS工艺下实现了90GS/s的采样率，功耗仅为667mW，解决了高速光通信中ADC采样率不足的问题。

💡 主要创新点

• 采用64路交织架构，结合SAR ADC的低功耗特性，实现了90GS/s的超高采样率。
• 在32nm数字SOI CMOS工艺中优化了时序和匹配，降低了交织带来的失配和噪声。

🏷 关键词

📄 原文摘要

Christian Menolfi1, Matthias Braendli1, Marcel Kossel1, Thomas Morf1, Toke Meyer Andersen1, Yusuf Leblebici2 IBM Research, Rüschlikon, Switzerland, EPFL, Lausanne, Switzerland 1 2 Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s Ethernet require ADCs with more than 50GS/s and at least 5 ENOB to enable complex equalization in the digital domain. SAR ADCs and interleaved ADCs made impressive progress in recent years. First CMOS ADCs with at least 6b and conversion rates exceeding 20GS/s were presented [1-3], proving that interleaved SAR ADCs are an optimal choice for high-speed ADCs with moderate resolution. We present an interleaved CMOS ADC architecture based on an asynchronous redundant SAR ADC core element. It was measured up to a sampling rate of 100GS/s and can be operated from a single supply voltage. At 90GS/s, the measured SNDR stays above 36.0dB SNDR up to 6.1GHz and

👥 作者与机构

Lukas Kull1,2, Thomas Toifl1, Martin Schmatz1, Pier Andrea Francese1,