A Reconfigurable Sense Amplifier with Auto-Zero Calibration and Pre-Amplification in 28nm CMOS

📋 论文概要

该论文提出了一种在28nm CMOS工艺下实现的可重构感测放大器，通过自动调零校准和预放大技术，解决了高性能SRAM中位线感测的鲁棒性问题，在工艺缩放和失配增加的情况下提高了感测速度与可靠性。

💡 主要创新点

• 提出可重构感测放大器架构，能够根据工作条件动态调整配置以优化性能。
• 集成自动调零校准机制，有效补偿工艺失配和偏移，提高感测精度。
• 采用预放大技术，在感测前放大位线差分信号，降低对位线摆幅的要求，提升感测速度。

🏷 关键词

📄 原文摘要

High-performance SRAMs are critical elements in microprocessors and SoCs. Fast and robust bitline sensing is a key requirement in such memories. With process scaling, increased mismatch in the sense amplifier (SA) circuit and increased Iread variation in the bitcell [1] have degraded sensing robustness. The fundamental tradeoff between sensing time and bitline read failures (Fig. 13.7.1) forces designers to heavily margin sensing time in order to guarantee sufficient bitline differential voltage prior to SA triggering. Previous research has improved SA robustness using pre-amplification circuits [2], capacitance-based offset cancellation [3-4], and redundancy [5]. However, most of these schemes target single-ended sensing (losing the benefit of common-mode rejection), incurring up to 60% area overhead or post-silicon tuning costs. This work presents an area-efficient and variation-tolerant small-signal

👥 作者与机构

Bharan Giridhar, Nathaniel Pinckney, Dennis Sylvester, David Blaauw

University of Michigan, Ann Arbor, MI