An 860µW 2.1-to-2.7GHz All-Digital PLL-Based Frequency Modulator with a DTC-Assisted Snapshot TDC for WPAN (Bluetooth Smart and ZigBee) Applications

📋 论文概要

提出了一种用于WPAN（蓝牙）的860µW、2.1-to-2.7GHz全数字PLL频率调制器，采用DTC辅助的快照TDC和DC耦合缓冲器，降低了功耗和噪声馈通，解决了低功耗无线通信中的频率调制问题。

💡 主要创新点

• 采用DC耦合DCO缓冲器代替AC耦合，通过数字控制PMOS/NMOS比校准占空比，降低功耗和噪声馈通。
• 使用基于传输门的动态分频器，实现高速、低功耗、低电压操作。
• 引入DTC辅助的快照TDC，提高时间分辨率并降低功耗。

📄 原文摘要

at Analog Devices, Limerick, Ireland 1 Using a DC-coupled buffer instead of an AC-coupled one, power consumption and noise feed-through into the DCO are reduced. The VTC of the DC-coupled DCO buffer can be varied by digitally controlling the device ratio of PMOS to NMOS (Wp/Wn) of the inverter to cover process variation, and is calibrated by monitoring the duty-cycle of the output signal. A transmission-gate-based dynamic divider is used for its high-speed, low-power, and low-voltage operation. Since the divider (/2) reduces the ADPLL operation rate, the phase incrementer can be realized by an asynchronous counter to reduce power consumption. The outputs of the counter are then synchronized by adding appropriate delays before being sampled by CKR to generate the integer part of

👥 作者与机构

Vamshi Krishna Chillara1,2*, Yao-Hong Liu1, Bindi Wang1,2, Ao Ba1,

Maja Vidojkovic1, Kathleen Philips1, Harmke de Groot1, Robert Bogdan Staszewski2 Holst Centre/imec, Eindhoven, The Netherlands, Delft University of Technology, Delft, The Netherlands *now