A 16nm 128Mb SRAM in High-κ Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications

📋 论文概要

该论文在16nm高κ金属栅极FinFET工艺中实现了一款128Mb SRAM，通过写入辅助电路实现了低VMIN工作。针对FinFET器件量化尺寸对传统6T-SRAM单元缩放的挑战，提出了优化方案。

💡 主要创新点

• 在16nm FinFET工艺中成功实现128Mb SRAM，验证了该工艺在大容量嵌入式存储中的可行性。
• 提出写入辅助电路(Write-Assist Circuitry)，有效降低SRAM的VDDMIN，适用于低电压应用。
• 针对FinFET器件量化通道宽度和长度的局限，进行了针对性的6T-SRAM单元设计和优化。

🏷 关键词

📄 原文摘要

Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang TSMC, Hsinchu, Taiwan FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better subthreshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve better performance with lower SRAM VDDMIN. However, the quantized sizing of the channel width and length has drawbacks for conventional 6T-SRAM bitcell scaling. To minimize the bitcell area of the high-density SRAM bitcell, the number of fins (setting the channel width, W) of the pull-up PMOS (PU), passgate NMOS (PG) and pull-down NMOS (PD) transistors must be selected as 1:1:1. Since PU, PG, and PD have the same channel length (L), the ratio in geometry between the PU transistor and the PG transistor is equal to one. With

👥 作者与机构

Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao,