⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种采用InP BiCMOS技术的双开关跟踪保持放大器（THA），实现了30GS/s的采样率和19dBm的IIP3，解决了高速CMOS ADC在高频下线性度快速退化的问题，适用于100Gb/s光通信系统。
Thomas C. Oh4, James F. Buckwalter2 Qualcomm, San Diego, CA, University of California, San Diego, La Jolla, CA, 3 Peregrine Semiconductor, San Diego, CA, 4 HRL Laboratories, Malibu, CA 1 2 High-speed track-and-hold amplifier (THA) circuits are critical for high-speed, high-resolution data converters, particularly in emerging 100Gb/s optical communication systems. High-speed CMOS analog-to-digital converters (ADCs) have been demonstrated to 56GS/s, but the linearity tends to rapidly degrade at high frequency [1]. The use of a high-speed THA can broaden the frequency response, improve the distortion performance, and mitigate some of the timing requirements for high-speed time-interleaved ADCs. Recent THA work has leveraged high-fmax Indium Phosphide (InP) HBTs to implement 50GS/s track-and-hold amplifiers [2]. Nonetheless, a two-chip solution consisting of an InP THA and time-interleaved CMOS ADCs is extremely difficult to package while
Timothy D. Gathman1,2, Kristian N. Madsen2,3, James C. Li4,