A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS

📋 论文概要

本文提出了一种1.62GS/s的时间交织SAR ADC，采用数字后台失配校准技术，有效抑制了交织杂散至70dB以下，解决了高速ADC中通道间失配导致的性能下降问题。

💡 主要创新点

• 提出数字后台失配校准算法，无需中断正常转换即可实时校正通道间增益、偏移和时序失配
• 实现了1.62GS/s的高速采样率，同时保持低于70dB的交织杂散水平，显著提升了时间交织ADC的线性度

🏷 关键词

📄 原文摘要

Sarah Verhaeren1, Emmanuel Rouat1, Pascal Urard1, Stéphane Le Tual1, Dimitri Goguet1, Caroline Lelandais-Perrault2, Philippe Benabes2 STMicroelectronics, Crolles, France, Supélec, Gif-sur-Yvette, France 1 2 Today’s applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed

👥 作者与机构

Nicolas Le Dortz1,2, Jean-Pierre Blanc1, Thierry Simon1,