⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种25.6Gb/s的差分与DDR4/GDDR5双模式发射器，采用数字时钟校准技术，在22nm CMOS工艺中实现。解决了高速内存接口中不同标准（DDR4和GDDR5）的兼容性问题，并提升了信号完整性。
Joseph Kennedy, Gokce Keskin, Tawfiq Musah, Sudip Shekhar*, Rajesh Inti, Shreyas Sen, Mozhgan Mansuri, Clark Roberts, Bryan Casper Intel, Hillsboro, OR *now with University of British Columbia, Vancouver, Canada A wide range of memory configurations exist in today’s high-speed digital systems to meet platform-specific bandwidth, power, capacity, and cost constraints. In the near term, DDR4 and GDDR5 are expected to meet the needs of server, client, graphics and mobile platforms [1]. Differential signaling with high-speed serial I/O enhancements will potentially continue I/O performance scaling for post-DDR4 and future buffered memory solutions. A unified memory interface that can meet the signaling requirements of all these memory standards offers several benefits: reduced cost and design time, greater platform design flexibility, and a smoother transition from DDR4/GDDR5 to a high-speed differential memory interface [2]. This paper presents a dual-mode TX that
Tzu-Chien Hsueh, Ganesh Balamurugan, James Jaussi, Sami Hyvonen,