A Scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC Decoder for 60GHz Wireless Networks in 28nm UTBB FDSOI

📋 论文概要

本文提出了一种支持IEEE 802.11ad标准的可扩展LDPC解码器，在28nm UTBB FDSOI工艺上实现1.5至6Gb/s的吞吐量，功耗仅为6.2至38.1mW。它解决了60GHz无线网络中高速率、多码率解码的高功耗问题，实现了性能与能效的平衡。

💡 主要创新点

• 采用28nm UTBB FDSOI工艺，通过体偏置技术实现低电压操作，大幅降低功耗。
• 提出可扩展架构，支持1.5/3/6Gb/s三种吞吐量和多种码率（1/2, 5/8, 3/4, 13/16），满足IEEE 802.11ad标准需求。
• 通过高效的数据流和存储器设计，在保持高吞吐量的同时将功耗控制在毫瓦级。

🏷 关键词

📄 原文摘要

France, 3 EPFL, Lausanne, Switzerland 1 2 Low-density parity-check (LDPC) codes in modern wireless communications are rate- and throughput-scalable, and despite their complexity, decoding them requires low power consumption. The IEEE 802.11ad standard for Gb/s wireless LANs in the 60GHz band requires an implementation of an LDPC encoder/decoder with throughputs of 1.5, 3, and 6Gb/s, with code rates of 1/2, 5/8, 3/4 and 13/16 [1]. Previous implementations of decoders for these throughputs and levels of reconfiguration have power consumptions on the order of the rest of the baseband processing [2,3]. This paper presents a fully compatible IEEE 802.11ad LDPC decoder in 28nm ultra-thin body and BOX fullydepleted SOI (UTBB FDSOI) technology with a power consumption that is a

👥 作者与机构

Matthew Weiner1, Milovan Blagojevic1,2,3, Sergey Skotnikov4,

Andreas Burg4, Philippe Flatresse3, Borivoje Nikolic1 University of California, Berkeley, CA, Institute Supérieur d'Electronique de Paris, Paris, France 2 STMicroelectronics, Crolles,