A 12×5 Two-Dimensional Optical I/O Array for 600Gb/s Chip-to-Chip Interconnect in 65nm CMOS

📋 论文概要

该论文提出了一种12×5二维光学I/O阵列，用于实现600Gb/s的芯片间互连，解决了传统电互连在带宽和功耗方面的瓶颈问题。通过在65nm CMOS工艺中集成光学收发器阵列，实现了高密度、高带宽的光学互连。

💡 主要创新点

• 提出12×5二维光学I/O阵列架构，实现60通道并行传输，总带宽达600Gb/s。
• 采用光学通孔（optical vias）技术耦合透镜阵列，提高了光耦合效率并简化了封装。
• 在65nm CMOS工艺中集成光学收发器，实现了低功耗、高密度的芯片间互连方案。

🏷 关键词

📄 原文摘要

The aggregate bandwidth required between two processors, for example, is expected to extend into the terabit-per-second range or higher [1]. Bandwidth is typically the bottleneck in such situations. Optical interconnect technologies have the potential to overcome bandwidth limitations for such chip-to-chip or board-toboard communication [2] through increased channel speed and/or multiple channels. Channel speeds have reached 25Gb/s and higher [3,4], in addition, a 24-channel transmitter and 24-channel receiver is disclosed [5] that employs optical vias in silicon to couple the lens array. Two possible structures to implement a multichannel system are shown in Fig. 8.2.1. A conventional multichannel architecture places the laser diode drivers (LDD) and VCSELs on the

👥 作者与机构

Hiroshi Morita, Koki Uchino, Eiji Otani, Hiizu Ohtorii, Takeshi Ogura,

Kazunao Oniki, Shuichi Oka, Shusaku Yanagawa, Hideyuki Suzuki Sony, Tokyo, Japan High-performance systems require high-bandwidth interconnections