A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

📋 论文概要

本文提出了一款69.5mW功耗、20GS/s采样率的6位时间交织ADC，采用32nm CMOS SOI工艺，集成了嵌入式时间-数字校准技术。该设计解决了传统时间交织ADC因通道间时序偏差导致的性能下降问题，通过片上校准实现了低功耗高速运行。

💡 主要创新点

• 提出嵌入式时间-数字校准技术，无需额外参考信号或软件傅里叶分析，直接校准时序偏差。
• 采用分布式跟踪保持器替代高功耗的两级跟踪保持器，结合校准技术满足时序偏差要求。

🏷 关键词

📄 原文摘要

Low-power time-interleaved ADCs with high sampling rates of over 10GS/s are in high demand for wireline communication systems. However, the timeinterleaved channels suffer from process mismatch, particularly for timing skew. Although a power-consuming two-rank track-and-hold (T/H) can prevent such timing-skew problems, distributed T/Hs can be used for lower-power operation with timing-skew calibration to meet the skew specifications of 200fsrms for 6b resolution and 10GHz input signals. Instead of using software calibration with Fourier analysis [1-3], requiring a special input reference signal [4], or relying on the statistics of the input signal [5], this work presents a low-complexity on-chip background calibration technique to reduce gain, offset, and delay mismatches between channels. This enables small-size transistors to be used in comparators and clock delivery circuits to avoid serious noise coupling and save considerable

👥 作者与机构

Vanessa Hung-Chu Chen, Lawrence Pileggi

Carnegie Mellon University, Pittsburgh, PA