A 5mW CT ΔΣ ADC with Embedded 2nd-Order Active Filter and VGA Achieving 82dB DR in 2MHz BW

📋 论文概要

这篇论文提出了一种嵌入二阶有源滤波器和可变增益放大器（VGA）的连续时间ΔΣ ADC，解决了传统CTDSM中信号传输函数（STF）形状不可独立控制导致难以处理带外干扰的问题。该设计在2MHz带宽内实现了82dB的动态范围，功耗仅为5mW。

💡 主要创新点

• 提出将二阶有源滤波器和VGA嵌入到连续时间ΔΣ调制器中，实现STF的独立控制，有效抑制带外干扰。
• 在不增加额外滤波级的情况下，通过在调制器内部集成滤波和增益控制，降低了系统功耗并提高了动态范围。

🏷 关键词

📄 原文摘要

IIT Madras, Chennai, India Conventional continuous-time delta-sigma modulator (CTDSM) architectures do not allow independent control of the shape and bandwidth of the signal transfer function (STF), since the STF is simply a by-product of NTF synthesis. This is particularly troublesome when the input to the CTDSM consists of large out-ofband interferers; handling them without saturating the quantizer needs larger inband DR, leading to increased power dissipation. A solution to this problem is to use a filter upfront to attenuate interferers. Alternatively [1], the filter can be moved into the CTDSM loop. In [1], a 1st-order RC filter was used to “tame” the STF peak of a cascade of integrators with feedforward summation (CIFF) DSM. Apart from the limited selectivity offered by a 1st-order filter, an active feedback path was necessary to stabilize the loop. The CTDSM in our work obtains an STF

👥 作者与机构

Radha Rajan, Shanthi Pavan