A 1.5mW 68dB SNDR 80MS/s 2× Interleaved SARAssisted Pipelined ADC in 28nm CMOS

📋 论文概要

该论文提出了一种在28nm CMOS工艺下实现的1.5mW功耗、68dB SNDR、80MS/s采样率的2倍交错SAR辅助流水线ADC，解决了高速高精度SAR ADC功率效率低的问题，并包含了主动参考发生器、时钟发生器和编码器的全部功耗。

💡 主要创新点

• 采用SAR辅助流水线架构结合2倍交错，在80MS/s采样率下实现了68dB SNDR，同时保持极低功耗（1.5mW）。
• 将主动参考发生器、时钟发生器和编码器的功耗全部计入，区别于大多数仅报告核心ADC功耗的SAR ADC设计。

🏷 关键词

📄 原文摘要

sampling speed of recently reported SAR ADCs have increased to 11+ ENOB at 50 to 100MS/s [1,2]; however, power efficiency has unfortunately suffered when compared to lower-resolution, lower-speed ADCs. This design targets the same high speed and resolution while simultaneously achieving power efficiency previously associated only with low-speed, low-resolution ADCs. Furthermore, the power reported includes the consumption from the active reference generator, clock generator and encoder (since this is an industrial SoC), differentiating it from the majority of reported SAR ADCs. A dynamic residue amplifier with excellent noise-filtering properties, embedded in a pipelined architecture, is a key power-saving technique. In addition, an energy-efficient switched-capacitor (SC) DAC is obtained by using a small fraction of

👥 作者与机构

Frank van der Goes1, Chris Ward1, Santosh Astgimath2, Han Yan1,

Jeff Riley1, Jan Mulder1, Sijia Wang1, Klaas Bult1 Broadcom, Bunnik, The Netherlands, Wolfson Microelectronics, Edinburgh, United Kingdom 1 2 The resolution and