A 130mW 20Gb/s Half-Duplex Serial Link in 28nm CMOS

📋 论文概要

该论文提出了一种在28nm CMOS工艺下实现的20Gb/s半双工串行链路，旨在解决CPU/GPU间高带宽、低功耗的芯片间通信需求。通过优化均衡技术，在20Gb/s速率下实现了130mW的低功耗，有效应对了高频信道损耗和阻抗不连续问题。

💡 主要创新点

• 采用半双工双向链路架构，在20Gb/s速率下实现130mW的低功耗，能效比优异。
• 针对高频信道损耗和阻抗不连续，设计了高效的均衡方案，确保可靠传输。

🏷 关键词

📄 原文摘要

Sanjeev Maheswari, Ratnakar Dadi, Arif Amin, Gautam Bhatia, Peter Mills, Ahmed Ragab, Edward Lee nVidia, Santa Clara, CA As the processing power and clock rate of CPUs and GPUs increase, there is a need for increased I/O bandwidth to enable chip-to-chip communication [1]. I/O pin limitations demand faster links at low power to enable integration of high chip-to-chip bandwidth. However, the channel losses and impedance discontinuities increase at high data rates making it difficult to equalize the channel at low power. In this work, we target reliable, differential, bi-directional links at 20Gb/s over 6” FR4 PCB trace and flip-chip packages with a total loss budget of 20dB at Nyquist. In a half-duplex link, one TX and RX are connected on each side and the link direction can be turned around by the controller. A linkturnaround latency of <10ns is achieved by placing several key circuits on standby when not in use and by designing fast bias circuits. When fast turnaround is not required,

👥 作者与机构

Vishnu Balan, Olakanmi Oluwole, Gregory Kodani, Charlie Zhong,