A Pulse-Position-Modulation Phase-Noise-Reduction Technique for a 2-to-16GHz Injection-Locked Ring Oscillator in 20nm CMOS

📋 论文概要

该论文提出了一种基于脉冲位置调制（PPM）的相位噪声降低技术，用于2至16GHz注入锁定环形振荡器，解决了传统环形振荡器相位噪声高、面积大的问题，实现了宽频率范围的低抖动时钟生成。

💡 主要创新点

• 提出脉冲位置调制（PPM）技术，通过调制注入脉冲的位置来降低环形振荡器的相位噪声。
• 实现了2至16GHz的宽频率范围覆盖，适用于FPGA中的高速收发器。
• 采用20nm CMOS工艺，相比LC振荡器显著减小了面积，提高了集成度。

🏷 关键词

📄 原文摘要

Wayne Fang2, Ali M. Niknejad1, Jafar Savoj2, Ken Chang2 University of California, Berkeley, CA, Xilinx, San Jose, CA 1 2 High-speed transceivers embedded inside FPGAs require softwareprogrammable clocking circuits to cover a wide range of data rates across different channels [1]. These transceivers use high-frequency PLLs with LC oscillators to satisfy stringent jitter requirements at increasing data rates. However, the large area of these oscillators limits the number of independent LC-based clocking sources and reduces the flexibility offered by the FPGA. A ring-based PLL occupies smaller area but produces higher jitter. With injectionlocking (IL) techniques [2-3], ring-based oscillators achieve comparable performance with their LC counterparts [4-5] at frequencies below 10GHz. Moreover, addition of a PLL to an injection-locked VCO (IL-PLL) provides injection-timing calibration and frequency tracking against PVT [3,5].

👥 作者与机构

Jun-Chau Chien1, Parag Upadhyaya2, Howard Jung2, Stanley Chen2,