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该论文提出了一种背景校准技术，用于控制数字锁相环（DPLL）的带宽，解决了因工艺、电压、温度变化以及频率调谐范围变化导致的带宽不稳定的问题。通过校准时间/数字转换器（TDC）和数控振荡器（DCO）的增益，实现了带宽的精确控制。
parameters that are subject to process, temperature and voltage spreads, as well as to variations along the frequency-tuning range. Even in digital PLLs, which rely on a digital loop filter, the bandwidth still depends on the gains of two mixed-signal building blocks, namely the time/digital converter (TDC) and the digitally-controlled oscillator (DCO), that have conversion characteristics that are not well-controlled. The situation is even more cumbersome employing a singlebit TDC, often referred to as bang-bang phase detector (BBPD), where the linearized gain is inversely proportional to the input jitter [1]. An accurate and repeatable value of the PLL bandwidth, and in the general of the frequency response, is essential to meet several specifications, such as stability margin,
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Politecnico di Milano, Milan, Italy The bandwidth of a phased-locked loop (PLL) is dependent on several analog