A 340mV-to-0.9V 20.2Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16×16 Network-onChip in 22nm Tri-Gate CMOS

📋 论文概要

该论文提出了一种在22nm三栅CMOS工艺下实现的16×16网络片上系统，采用源同步混合包/电路交换架构，工作电压范围从340mV到0.9V，总带宽达到20.2Tb/s。旨在解决传统同步NoC因全局时钟或时钟域交叉FIFO带来的高功耗和面积开销问题，为百核级异构计算提供高能效通信基础。

💡 主要创新点

• 提出源同步混合包/电路交换架构，结合两者优势，降低全局时钟的功耗和面积开销。
• 实现宽电压范围（340mV-0.9V）工作，支持动态电压频率调节，提升能效。
• 在22nm三栅CMOS工艺下达到20.2Tb/s的高聚合带宽，满足大规模核心间通信需求。

🏷 关键词

📄 原文摘要

Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De Intel, Hillsboro, OR Energy-efficient networks-on-chip (NoCs) are key enablers for exa-scale computation by shifting power budget from communication toward computation. As core counts scale into the 100s, on-chip interconnect fabrics must support increasing heterogeneity and voltage/clock domains. Synchronous NoCs require either a single clock distributed globally or clock-crossing data FIFOs between clock domains [1]. A global clock requires costly full-chip margining and significant power and area for clock distribution, while synchronizing data FIFOs add power, performance, and area overhead per clock crossing. Source-synchronous NoCs mitigate these penalties by forwarding a local clock along with each packet, but still suffer from high data storage power due to packet switching. Circuit switching removes intra-route data storage, but

👥 作者与机构

Gregory Chen, Mark A. Anders, Himanshu Kaul, Sudhir K. Satpathy,