A 20-to-1000MHz ±14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS

📋 论文概要

该论文提出了一种20至1000MHz、±14ps峰峰值抖动的可重构多输出全数字时钟发生器，采用开环分数分频架构，解决了多模块SoC中不同时钟需求（如动态频率缩放、扩频时钟和快速功率循环）的灵活生成问题。

💡 主要创新点

• 提出开环分数分频架构，避免了传统PLL的反馈环路，实现了快速频率切换和低抖动。
• 实现多输出可重构时钟生成，支持独立频率和相位调整，满足SoC中不同模块的时钟需求。
• 采用全数字实现，提高了工艺可移植性和抗噪声能力。

🏷 关键词

📄 原文摘要

digital, and mixed-signal functions. They contain a wide variety of modules such as multicore processors, memories, I/O interfaces, power management, and wireless transceivers. Each module has its own unique clock requirements to maximize the overall system performance. For example, dynamic frequency scaling (DFS) saves processor power, spread spectrum clocking (SSC) reduces electromagnetic interference (EMI), and rapid power cycling between idle and active states allows energy-proportional operation. A conventional analog integer-N phase-locked loop (PLL)-based clock generation unit (CGU) occupies large area, has a long lock time, and its output frequency resolution is limited by the reference clock frequency. While the digital fractional-N PLL-based CGU in

👥 作者与机构

Ahmed Elkholy1, Amr Elshazly2, Saurabh Saxena1,

Guanghua Shu1, Pavan Kumar Hanumolu1 University of Illinois, Urbana, IL, 2Intel, Hillsboro, OR 1 Modern systems-on-chips (SoCs) perform many diverse analog,