A Sub-1.75W Full-Duplex 10GBASE-T Transceiver in 40nm CMOS

📋 论文概要

本文描述了一款用于四端口10GBASE-T收发器芯片的模拟前端(AFE)，在40nm CMOS工艺下实现了低于1.75W的全双工10Gb/s以太网传输。该设计解决了高密度网络交换机对小尺寸、高能效收发器的需求。

💡 主要创新点

• 采用低功耗模拟前端设计，实现每端口低于1.75W的功耗，适用于四端口集成。
• 通过紧凑的电路布局和封装技术（23×23mm² BGA），在40nm工艺下实现小尺寸全双工10GBASE-T收发器。

🏷 关键词

📄 原文摘要

Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M.L. van der Goes, Klaas Bult Broadcom, Bunnik, The Netherlands The IEEE802.3an 10GBASE-T standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. For the implementation of high-density 10GBASE-T network switches, highly integrated transceivers are required that have both a small form factor and high power efficiency. This paper describes an analog front-end (AFE) that is used in a quad-port 10GBASE-T transceiver chip. The small form factor of the AFE allows for the use of a 23×23mm2 BGA package, enabling implementation of 48-port switches with all transceivers in a single row on the PCB pitch-matched to the RJ45 connector arrays. The design achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR, and >60dBc receiver SFDR up to 400MHz. It occupies an area of 15.1mm2 per port in a 40nm CMOS process. At 100m full 10Gb/s traffic, the AFE

👥 作者与机构

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu,