A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS

📋 论文概要

该论文提出了一种在40nm CMOS工艺下实现的10位200kS/s子区间SAR ADC，其能效达到0.85fJ/conversion-step，主要面向无线传感器网络和医疗电子设备等需要长电池寿命的应用。通过采用子区间架构和低功耗电路技术，实现了高能效的模数转换。

💡 主要创新点

• 采用子区间SAR架构，结合低功耗电容DAC切换方法，显著降低了每次转换的能量消耗。

📄 原文摘要

Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications by using an energy-efficient ADC. A successive-approximation register (SAR) architecture, mostly composed of digital circuits, can achieve low power under low supply voltages [1,2]. Power consumption can be decreased by using either an energy-efficient capacitive-DAC switching method [1] or a low-power comparator with a majority voting technique [2]. In this work, a small coarse ADC resolves the MSB bits. Then, a detect-and-skip algorithm and an aligned switching technique are used to reduce the big fine DAC switching energy. The comparator power is also decreased by utilizing a low-power comparator during coarse conversion and a low-noise comparator during fine conversion. As a result, its FoM performance

👥 作者与机构

Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen

National Taiwan University, Taipei, Taiwan