A 23Mb/s 23pJ/b Fully Synthesized True-RandomNumber Generator in 28nm and 65nm CMOS

📋 论文概要

该论文提出了一种全合成设计的真随机数发生器(TRNG)，利用物理随机性作为熵源，在28nm和65nm CMOS工艺中实现。通过异步时钟采样和RC滤波技术，实现了23Mb/s的高吞吐率和23pJ/b的低能耗，解决了传统TRNG设计复杂、功耗高的问题。

💡 主要创新点

• 采用全合成设计流程，无需定制电路，提高了设计效率和可移植性
• 通过异步时钟采样和RC滤波技术抑制电源噪声，提升随机数质量
• 在28nm和65nm两种工艺下验证，展示了工艺可扩展性

🏷 关键词

📄 原文摘要

David Blaauw, Dennis Sylvester locking the oscillation and impacting collapse event time. To measure noise amplitude on-chip, an asynchronous clock samples the supply voltage, compares it with an external reference voltage, and increments a counter accordingly. With sufficient samples (214 here) the noise amplitude can be determined from the counter value. In addition, an RC filter with a 210MHz corner frequency was designed to mitigate the impact of supply noise (Fig. 16.3.3). University of Michigan, Ann Arbor, MI True random number generators (TRNGs) use physical randomness as entropy sources and are heavily used in cryptography and security [1]. Although hardware TRNGs provide excellent randomness, power consumption and design complexity are often high. Previous work has demonstrated TRNGs based on a resistor-amplifier-ADC chain [2], oscillator jitter [1], metastability [3-5] and other device noise [6-7]. However, analog designs suffer from variation and

👥 作者与机构

Kaiyuan Yang, David Fick, Michael B. Henry, Yoonmyung Lee,