A 1000fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array and Self-Organizing Map Neural Network

📋 论文概要

该论文提出了一种基于动态可重构混合架构的1000fps视觉芯片，集成了图像传感器和并行图像处理器，解决了高速视觉识别应用中对高帧率和强大处理能力的需求。通过结合像素并行和行并行SIMD阵列处理器以及嵌入式微处理器，实现了低、中、高级图像处理的高效协同。

💡 主要创新点

• 提出了一种动态可重构的混合架构，结合了PE阵列和自组织处理单元，实现了灵活的图像处理。
• 实现了1000fps的高速视觉处理，同时集成了图像传感器和并行处理器，提升了系统集成度和处理效率。

🏷 关键词

📄 原文摘要

that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the von Neumann bottleneck of the MPU. As a

👥 作者与机构

Cong Shi1,2, Jie Yang1, Ye Han1, Zhongxiang Cao1, Qi Qin1,

Liyuan Liu1, Nan-Jian Wu1, Zhihua Wang2 Chinese Academy of Sciences, Beijing, China, Tsinghua University, Beijing, China 1 2 A vision chip is a high-speed and compact vision system