A 28Gb/s 1pJ/b Shared-Inductor Optical Receiver with 56% Chip-Area Reduction in 28nm CMOS

📋 论文概要

该论文提出了一种共享电感结构的光接收机，在28nm CMOS工艺下实现了28Gb/s的数据率和1pJ/b的能效，同时将芯片面积减少了56%，解决了传统电感峰化占用面积大的问题。

💡 主要创新点

• 提出共享电感结构，有效减少芯片面积56%
• 实现28Gb/s高速率且能效仅1pJ/b
• 在28nm CMOS工艺下验证了面积与性能的优化

🏷 关键词

📄 原文摘要

high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at high frequencies, requiring simpler equalization circuits than electrical links. The energy-efficiency of optical links can thus be significantly improved [1-5]. Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes. In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offsetcan

👥 作者与机构

Tsung-Ching Huang1, Tao-Wen Chung2, Chan-Hong Chern1,

Ming-Chieh Huang1, Chih-Chang Lin1, Fu-Lung Hsueh3 TSMC Design Technology, San Jose, CA, 2nVidia, San Jose, CA, TSMC, Hsinchu, Taiwan 1 3 Next-generation