Wide-Frequency-Range Resonant Clock with On-the-Fly Mode Changing for the POWER8TM Microprocessor

📋 论文概要

本文为IBM POWER8微处理器设计了一种宽频范围谐振时钟，通过在线模式切换实现两种谐振模式和非谐振模式，在2.5GHz至5GHz以上频率范围内节省时钟功耗。该设计由12个chiplet组成，每个chiplet包含一个核心和L2缓存的谐振时钟网格，以及L3缓存的半频率非谐振时钟网格。

💡 主要创新点

• 提出了一种支持两种谐振模式和一种非谐振模式的谐振时钟架构，能够根据频率需求在线切换模式，从而在宽频率范围内优化功耗。
• 采用多chiplet结构，每个chiplet独立管理其核心和L2缓存的谐振时钟网格，L3缓存使用半频率非谐振时钟，实现灵活的分区时钟管理。
• 通过门控本地时钟缓冲器（LCB）来测量全局时钟功耗，提供精确的功耗评估方法。

🏷 关键词

📄 原文摘要

4IBM STG, Williston, VT, 5IBM STG, Raleigh, NC 1 3 A resonant-clock design for the IBM POWER8 processor core was implemented with 2 resonant modes (and a non-resonant mode), saving clock power over a wide frequency range from 2.5GHz to more than 5GHz. The POWER8 microprocessor is composed of 12 chiplets, each containing a single resonant clock grid for one core and its L2 cache, and a half-frequency, non-resonant clock grid for the L3 cache. The clock grids drive the local clock buffers (LCBs) that in turn drive the latches. The LCBs are gated off to measure the global clock power from the PLL to the LCBs. The resonant core communicates synchronously with the L3, requiring low skew between the domains. The chip

👥 作者与机构

Phillip Restle1, David Shan2, David Hogenmiller2, Yong Kim2,

Alan Drake3, Jason Hibbeler4, Thomas Bucelot1, Gregory Still5, Keith Jenkins1, Joshua Friedrich2 IBM Research, Yorktown Heights, NY, 2IBM STG, Austin, TX, IBM Research, Austin, TX,