Three-Dimensional 128Gb MLC Vertical NAND FlashMemory with 24-WL Stacked Layers and 50MB/s High-Speed Programming are reprogrammed in the next program pulse. As a result, the wider programmed

📋 论文概要

该论文提出了一种采用24层字线堆叠的三维128Gb多层单元(MLC)垂直NAND闪存，通过优化工艺和设计实现了50MB/s的高速写入吞吐量。解决了三维NAND闪存中因快速去陷阱导致的阈值电压分布展宽问题，有效提高了存储密度和编程速度。

💡 主要创新点

• 采用24层字线堆叠的三维垂直NAND结构，实现了128Gb的高密度MLC存储。
• 针对快速去陷阱引起的阈值电压分布恶化，通过工艺优化抑制了Vth分布展宽。
• 实现了50MB/s的高速写入性能，显著提升了三维NAND闪存的编程吞吐量。

🏷 关键词

📄 原文摘要

with performance of 50MB/s write throughput. Ki-Tae Park, Jin-man Han, Daehan Kim, Sangwan Nam, Kihwan Choi, Min-Su Kim, Pansuk Kwak, Doosub Lee, Yoon-He Choi, Kyung-Min Kang, Myung-Hoon Choi, Dong-Hun Kwak, Hyun-wook Park, Sang-won Shim, Hyun-Jun Yoon, Doohyun Kim, Sang-won Park, Kangbin Lee, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jeunghwan Park, Jinho Ryu, Donghyun Kim, Kyungwa Yun, Joonsoo Kwon, Seunghoon Shin, Dongkyu Youn, Won-Tae Kim, Taehyun Kim, Sung-Jun Kim, Sungwhan Seo, Hyung-Gon Kim, Dae-Seok Byeon, Hyang-Ja Yang, Moosung Kim, Myong-Seok Kim, Jinseon Yeon, Jaehoon Jang, Han-Soo Kim, Woonkyung Lee, Duheon Song, Sungsoo Lee, Kye-Hyun Kyung, Jeong-Hyuk Choi Another important design consideration is signal integrity for driving 3D memory array, especially for WL crosstalk caused by large capacitive coupling between WLs. Unlike line-to-line capacitive coupling between WLs in 2D planar NAND

👥 作者与机构

Vth distribution due to fast detrapping is reduced. Additionally, by incorporating, the cell characteristics mentioned above, a tightly programmed cell is realized