A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology

📋 论文概要

该论文实现了一个20GHz带宽、6位分辨率、10GS/s采样率、功耗32mW的时间交织SAR ADC，采用主从跟踪保持结构，在28nm UTBB FDSOI工艺上制造，实现了极小的芯片面积（0.009mm²），适用于高速数据通信。

💡 主要创新点

• 采用主从跟踪保持（Master T&H）结构，简化时间交织SAR ADC的时序约束，提升高速性能。
• 在28nm UTBB FDSOI工艺中实现极低功耗（32mW）和极小面积（每SAR 0.0007mm²），通过软聚合物基板和短压焊线优化封装。

🏷 关键词

📄 原文摘要

France 1 After quantization, each SAR stores its 6b word in 2 ping-pong 512-word RAMs running at 10GHz/8/2=625MHz. The total 8K words are finally read at low speed through a JTAG controller. The chip is fabricated in 28nm CMOS UTBB FDSOI technology, using 10 metal layers and MIM capacitors for decoupling. Each SAR occupies 50×13μm2 (0.0007mm2) and the complete ADC core is 80×115μm2 (0.009mm2). It is mounted in a soft polymeric substrate (PTFE) with a cavity for the die gluing, such that bonding wires are kept as small as possible (Fig. 22.3.7). 2 To sustain ever-growing data traffic, modern wireline communication devices (over copper or fiber optic media) require a high-speed ADC in their receive path to do the digital equalization, or to recover the complex-modulated information.

👥 作者与机构

Stéphane Le Tual1, Pratap Narayan Singh2, Christophe Curis3, Pierre Dautriche1

STMicroelectronics, Crolles, France, STMicroelectronics, Greater Noida, India, 3 STMicroelectronics, Grenoble,