A 0.012mm2 3.1mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Frequency Divider

📋 论文概要

该论文提出了一种面积为0.012mm²、功耗3.1mW的Bang-Bang数字分数-N锁相环（PLL），采用电源噪声抵消技术和Walking-One-P技术，以解决数字控制振荡器（DCO）对电源噪声敏感的问题，适用于SoC集成。

💡 主要创新点

• 提出电源噪声抵消技术，降低DCO对供电噪声的敏感度。
• 采用Walking-One-P技术，提高分数-N PLL的分辨率或线性度。
• 实现极小的芯片面积（0.012mm²）和低功耗（3.1mW），有利于SoC集成。

🏷 关键词

📄 原文摘要

recently due to their compatibility with advanced CMOS technology. However, there are two critical factors hindering their uptake in SoC products. One factor is that a digitally controlled oscillator (DCO) is highly sensitive to supply noise. A common solution is to apply voltage regulation or to adopt digital calibration

👥 作者与机构

Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin,

Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park Samsung Electronics, Yongin, Korea Digital phase-locked loops (DPLLs) [1-7] have received considerable attention