← 返回论文列表 📄 下载原文 PDF  ISSCC 2014 · 21.3
ISSCC 2014Session 21 · FREQUENCY GENERATION TECHNIQUESClocking & PLLs55nm CMOS

A 2GHz 130mW Direct-Digital Frequency Synthesizer with a Nonlinear DAC in 55nm CMOS

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一种2GHz、130mW的直接数字频率合成器,采用非线性DAC和55nm CMOS工艺,解决了传统DDFS中复杂度和功耗高的问题。通过创新的分段非线性DAC结构,实现了宽带宽、细频率分辨率和快速跳频特性。

💡 主要创新点

核心指标
2GHz, 130mW
工艺节点
55nm CMOS
重要性
发表年份
ISSCC 2014

🏷 关键词

直接数字频率合成器非线性DAC低功耗快速跳频55nm CMOS

📄 原文摘要

employed in many frequency-agile communication systems because of their wide bandwidth, fine frequency resolution, and fast frequency-hopping characteristics. Recent developments in DDFSs are towards enhancing performances through reduction of both complexity and power consumption [1-3]. The segmented nonlinear DAC (NLDAC) structures in [1,2] require additional coarse phase information for fine amplitude decoding with a complex decoder. Moreover, the quarter-sine-wave technique incorporated into the segmented NLDACs in [1,2] degrades spectral purity due to the need of the MSB shift DAC that introduces additional offset. Another scheme in [3] reduces complexity and power consumption by replacing the digital-based phase-to-amplitude converter with an analog-based converter,

👥 作者与机构

Taegeun Yoo1, Yun-Hwan Jung1, Hong Chang Yeoh1,2, Yong Sin Kim1,

Sung-Mo Kang3, Kwang-Hyun Baek1 Chung-Ang University, Seoul, Korea, 2Analog Devices, San Jose, CA, KAIST, Daejeon, Korea 1 3 Direct-digital frequency synthesizers (DDFSs) have been

分类:Clocking & PLLs · 年份:ISSCC 2014