⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一款采用28nm工艺的DSP，通过集成片上LDO供电，实现了高性能和能效的平衡，适用于移动应用。采用脉冲锁存器和统计优化技术，在宽工艺、电压和温度范围内保证鲁棒性，并显著降低时钟和数据功耗。
Xufeng Chen2, Maen Alradaideh1, Tom Wernimont1, Kartik Ayyar3, Dan Bui1, Dwight Galbi1, Allan Lester1, Willie Anderson1 Qualcomm, Austin, TX, 2Qualcomm, San Diego, CA, Qualcomm, Bangalore, India 1 The pulsed latches, also shown in Fig. 10.1.3, are used to implement most sequential elements. Statistical optimization techniques ensure robust operation across a wide range of process, voltage, and temperature conditions. Compared to conventional master-slave flip-flops, these pulsed latches consume significantly less clock and data power [5]. They also offer more data transparency, which improves performance. To reduce the variability caused by layout context effects, the pulse generator and up to 32 latches are bundled together in a single cell. The scan chain is internally connected from one bit to the next (so[n] to si[n+1]) using high-Vt gates. This ensures that the delay between successive bits exceeds the pulse width, in particular at low voltages.
Martin Saint-Laurent1, Paul Bassett1, Ken Lin2, Yuhe Wang2, Son Le2,