A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS

📋 论文概要

本文提出了一种采用子采样相位检测器（SSPD）的60GHz锁相环（PLL），在40nm CMOS工艺下实现了低相位噪声和低功耗。该PLL通过超谐波无源耦合的QVCO在0.9V电源下获得大摆幅和低相位噪声，同时利用SSPD降低带内相位噪声并允许关闭大部分分频链和电荷泵以节省功耗。

💡 主要创新点

• 采用子采样相位检测器（SSPD）降低带内相位噪声，并允许关闭大部分分频链和电荷泵以降低功耗。
• 使用超谐波无源耦合的QVCO，在0.9V低电源电压下实现大摆幅和低相位噪声。

🏷 关键词

📄 原文摘要

11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.9V supply. In-band phase noise is reduced thanks to the use of a sub-sampling phase detector (SSPD), earlier introduced for low-GHz PLLs [1]. As most of the divider chain and the charge pump (CP) can be powered down in the sub-sampling mode, power consumption is also reduced. The system architecture is shown in Fig. 21.4.1. The oscillator is a 60GHz QVCO for a direct-conversion transceiver. The synthesizer utilizes two loops, operated exclusively: classical PFD/CP integer-N and sub-sampling. The PFD/CP PLL forms a complete synthesizer with a static divide-by-2 and divide-by-3 circuit

👥 作者与机构

Viki Szortyka1,2, Qixian Shi1,2, Kuba Raczkowski1, Bertrand Parvais1,

Maarten Kuijk2, Piet Wambacq1,2 imec, Heverlee, Belgium, 2Vrije Universiteit Brussel, Brussels, Belgium 1 For high data-rate communication at 60GHz using the IEEE 802