⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种全集成包络消除与恢复（EER）CMOS功率放大器，工作于1.95GHz，通过集成包络/相位生成器解决了传统线性PA效率低的问题，实现了高功率效率与低失真。
Yoichi Kawano1, Noriaki Shirai2, Hideki Kano2, Masahiro Kudo2, Tomotoshi Murakami2, Tetsuro Tamura2, Shigeaki Kawai2, Shinji Yamaura2, Kazuo Suto2, Hiroshi Yamazaki1, Toshihiko Mori1 Fujitsu Laboratories, Kawasaki, Japan, Fujitsu Semiconductor, Yokohama, Japan 1 2 In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and high-power-efficiency CMOS power amplifier (PA). To improve the power efficiency of the conventional linear PA [1-4], an envelope tracking (ET) technique, which modulates supply voltage of a linear PA, has attracted attention. However, the published power efficiency, gain and output power are not sufficient for LTE applications [5], and its typical implementation requires an external supply modulator that is a high-speed power supply circuit [6]. Envelope elimination and restoration (EER) is an alternative supply modulation technique that can further
Kazuaki Oishi1, Eiji Yoshida1, Yasufumi Sakai1, Hideki Takauchi1,