A 780mW 4×28Gb/s Transceiver for 100GbE Gearbox PHY in 40nm CMOS

📋 论文概要

本文提出了一款用于100GbE Gearbox PHY的低功耗四通道20-28Gb/s收发器，采用40nm CMOS工艺，功耗仅780mW，解决了100Gb/s系统高功耗的挑战。

💡 主要创新点

• 采用低抖动发射机设计，降低时钟抖动对信号质量的影响。
• 使用半速率校准接收机切片器，提高接收灵敏度和数据恢复精度。

🏷 关键词

📄 原文摘要

centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that remains is the high power consumption of 100Gb/s systems. As mentioned in [1], power dissipation of the 100GbE gearbox transceiver is a significant portion of the optical module power. This paper demonstrates a low-power quad-lane 20-to-28Gb/s transceiver targeting 100GbE/40GbE (IEEE 802.3ba) standard. The transceiver features a low-jitter TX, half-rate calibrated RX slicer with folded active inductor and a wide-range PLL (20 to 28GHz) with low-power half-rate clock driver using programmable distributed inductors. It operates from a standard 0.9V supply

👥 作者与机构

Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang,

Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao Broadcom, Irvine, CA Network traffic speeds are increasing to meet the demands of data