A 14b 1GS/s RF Sampling Pipelined ADC with Background Calibration Fig. 29.3.4, and the LMS algorithm is used to estimate the correction coefficients using the recursive formula: Gen + k = Gen k − μ × Vd>n − k @ × Vd>n − k @ × Gen  k − VR >n@

📋 论文概要

该论文提出了一种14位1GS/s的RF采样流水线ADC，采用背景校准技术，利用LMS算法估计增益和记忆系数，以解决高速高精度ADC中的非线性误差和记忆效应问题。

💡 主要创新点

• 提出了一种适用于RF采样的流水线ADC架构，实现了14位分辨率与1GS/s采样率。
• 采用基于LMS算法的背景校准技术，同时估计级间增益和记忆系数，有效补偿了动态非线性误差。

🏷 关键词

📄 原文摘要

Scott Puckett1, Bryce Gray1, Carroll Speir1, Jonathan Lanford1, David Jarman1, Janet Brunsilius2, Peter Derounian1, Brad Jeffries1, Ushma Mehta1, Matt McShea1, Ho-Young Lee3 Where Vd is the dither value, VR is the residue of the stage being calibrated and μ is the algorithm step size. Gen,k is the estimate of the gain coefficient of the kth past sample on the present nth sample. If k=0, then Gen,0 is the coefficient for the inter-stage gain and settling error. If k>0, then Gen,k is a memory coefficient. Analog Devices, Greensboro, NC, 2Analog Devices, San Diego, CA, Analog Devices, Wilmington, MA The correction and equalization are done using FIR filters whose M taps are (Gen,k): M 1 3 We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory errors. An effective dithering technique is embedded in the calibration

👥 作者与机构

Ahmed M. A. Ali1, Huseyin Dinc1, Paritosh Bhoraskar1, Chris Dillon1,