⚡ 本页包含 AI 生成的分析内容，仅供参考
提出一种基于时间域的折叠-闪存ADC，采用电阻平均电压-时间放大器，在保持高采样率的同时降低比较器数量，从而减小面积和功耗。该ADC实现了2.2GS/s、7位分辨率、27.4mW功耗。
as 60GHz receivers, serial links, and high-density disk drive systems. Flash architectures have the highest conversion rate without employing time interleaving. Moreover, flash architectures have the lowest latency, which is often required in feedback-loop systems. However, the area and power consumption are exponentially increased by increasing the resolution since the number of comparators must be 2N. A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1,2]. Folding architectures were previously realized by generating a number of zero crossings with folding amplifiers. However, the conventional folding amplifiers consume a large amount of power
Masaya Miyahara, Ibuki Mano, Masaaki Nakayama,
Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan High-speed low-resolution ADCs are widely used for various applications, such