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本文介绍了AMD在28nm HKMG工艺下实现的x86-64双核CPU模块“Steamroller”,包含2.36亿晶体管,工作电压0.8-1.45V,模块面积29.47mm²,集成了独立整数核、指令解码单元、共享取指单元、浮点单元和2MB L2缓存,旨在提升能效和性能。
Stephen Kosonocky2, Robert S. Orefice1, Donald A. Priore1, Jonathan White1, Kathryn Wilcox1 AMD, Boxborough, MA, 2AMD, Fort Collins, CO, 3AMD, Austin, TX 1 The AMD two-core x86-64 CPU module, codenamed “Steamroller”, contains 236 million transistors implemented in 28nm high-κ metal gate (HKMG) bulk CMOS using 12 levels of metal. It is designed to operate from 0.8 to 1.45V. The CPU module occupies 29.47 mm2, which includes two independent integer cores, two instruction decode units and shared instruction fetch, floating-point, and 2MB 16-way L2 cache units (Fig. 5.5.7). Along with the second instruction decode unit, this design includes a larger shared 96KB 3-way instruction cache and a 10KB L2 branch target buffer for improved single-threaded performance and multi-threaded throughput compared to a previous 32nm AMD x86-64 CPU codenamed “Bulldozer” [1]. The module design contains 63 unique custom or compiled macros and 436,770
Kevin Gillespie1, Harry R. Fair III1, Carson Henrion2, Ravi Jotwani3,